Previous decoding circuits for emitter-coupled logic (ECL) memory required two "levels" of standard ECL gating to form the OR/NOR implementation of the address minterms. (A minterm of N variables is a Boolean product of these N variables, with each variable present in either its true or its complemented form.) In the logic circuitry previously used to decode the binary address inputs to an ECL memory, the address inputs are applied directly to ECL inverter circuits having load resistors connected between the collectors of the emitter-coupled transistors and the positive power supply conductor. This causes one stage of the delay of the decoding circuit. The differential collector outputs are coupled to the bases of emitter follower output transistors having multiple emitters. The multiple emitters from each address inverter are then emitter OR'ed (i.e., connected together) with the output emitters of the emitter followers of the other address inverters to provide the possible maxterms. (A number of N variables is a Boolean sum of these N variables, where each variable is present in either its true or its complemented form.) The maxterm nodes thus formed are than coupled to, respectively, 2.sup.N emitter coupled logic inverters to provide the 2.sup.N minterm functions, which provide the decoded outputs. Here N is the number of address inverters in the group. Because of circuit constraints and topological constraints, which reduce circuit speed, the maximum size of the maxterm groups is usually limited to three address input variables. The outputs of the "OR'ed" combination groups are provided as inputs to multiple input NOR gates, and the output is used to drive the selected memory row or column.